0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. RyuK. Ishida, M. Takamiya, Tadahiro Kuroda, H. Shinohara, T. Sakurai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

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