1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

Tadahiro Kuroda; Tetsuya Fujita; Yasushi Itabashi; Satohiko Kabumoto; Makoto Noda; Akira Kanuma

1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

Tadahiro Kuroda, Tetsuya Fujita, Yasushi Itabashi, Satohiko Kabumoto, Makoto Noda, Akira Kanuma

Research output: Contribution to journal › Conference article › peer-review

Abstract

The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 μm, 15 GHz bipolar process operate with a -2 V single power supply and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply. Gate stacking in ECL is effective in reducing power dissipation because complex logic can be implemented in a single gate with fewer current sources.

Original language	English
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	38
Publication status	Published - 1995 Feb 1
Externally published	Yes
Event	Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1995 Feb 15 → 1995 Feb 17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits",

abstract = "The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 μm, 15 GHz bipolar process operate with a -2 V single power supply and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply. Gate stacking in ECL is effective in reducing power dissipation because complex logic can be implemented in a single gate with fewer current sources.",

author = "Tadahiro Kuroda and Tetsuya Fujita and Yasushi Itabashi and Satohiko Kabumoto and Makoto Noda and Akira Kanuma",

year = "1995",

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journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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note = "Proceedings of the 1995 IEEE International Solid-State Circuits Conference ; Conference date: 15-02-1995 Through 17-02-1995",

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T1 - 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

AU - Kuroda, Tadahiro

AU - Fujita, Tetsuya

AU - Itabashi, Yasushi

AU - Kabumoto, Satohiko

AU - Noda, Makoto

AU - Kanuma, Akira

PY - 1995/2/1

Y1 - 1995/2/1

N2 - The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 μm, 15 GHz bipolar process operate with a -2 V single power supply and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply. Gate stacking in ECL is effective in reducing power dissipation because complex logic can be implemented in a single gate with fewer current sources.

AB - The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 μm, 15 GHz bipolar process operate with a -2 V single power supply and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply. Gate stacking in ECL is effective in reducing power dissipation because complex logic can be implemented in a single gate with fewer current sources.

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M3 - Conference article

AN - SCOPUS:0029255547

SN - 0193-6530

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JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Proceedings of the 1995 IEEE International Solid-State Circuits Conference

Y2 - 15 February 1995 through 17 February 1995

ER -

1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

Abstract

ASJC Scopus subject areas

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