2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda

doi:10.1109/JSSC.2009.2034431

2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.

Original language	English
Article number	5357556
Pages (from-to)	134-141
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	45
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2009.2034431
Publication status	Published - 2010 Jan 1

Keywords

Chip to chip
Inductive coupling
Memory stacking
SiP
Three-dimensional
Wireless interconnect

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2009.2034431

Cite this

@article{cd144e403f214a2097179d94a0765423,

title = "2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking",

abstract = "An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.",

keywords = "Chip to chip, Inductive coupling, Memory stacking, SiP, Three-dimensional, Wireless interconnect",

author = "Mitsuko Saito and Yasufumi Sugimori and Yoshinori Kohama and Yoichi Yoshida and Noriyuki Miura and Hiroki Ishikuro and Takayasu Sakurai and Tadahiro Kuroda",

year = "2010",

month = jan,

day = "1",

doi = "10.1109/JSSC.2009.2034431",

language = "English",

volume = "45",

pages = "134--141",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - 2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

AU - Saito, Mitsuko

AU - Sugimori, Yasufumi

AU - Kohama, Yoshinori

AU - Yoshida, Yoichi

AU - Miura, Noriyuki

AU - Ishikuro, Hiroki

AU - Sakurai, Takayasu

AU - Kuroda, Tadahiro

PY - 2010/1/1

Y1 - 2010/1/1

N2 - An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.

AB - An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.

KW - Chip to chip

KW - Inductive coupling

KW - Memory stacking

KW - SiP

KW - Three-dimensional

KW - Wireless interconnect

UR - http://www.scopus.com/inward/record.url?scp=73249143892&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=73249143892&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2009.2034431

DO - 10.1109/JSSC.2009.2034431

M3 - Article

AN - SCOPUS:73249143892

SN - 0018-9200

VL - 45

SP - 134

EP - 141

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 1

M1 - 5357556

ER -

2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this