3D clock distribution using vertically/horizontally-coupled resonators

Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)


    Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.

    Original languageEnglish
    Title of host publication2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
    Number of pages2
    Publication statusPublished - 2013 Apr 29
    Event2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
    Duration: 2013 Feb 172013 Feb 21

    Publication series

    NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    ISSN (Print)0193-6530


    Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
    Country/TerritoryUnited States
    CitySan Francisco, CA

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering


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