TY - GEN
T1 - 3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface
AU - Nakahara, Hiroshi
AU - Yasudo, Ryota
AU - Matsutani, Hiroki
AU - Amano, Hideharu
AU - Koibuchi, Michihiro
N1 - Funding Information:
This work is partially supported by JSPS KAKENHI S grant number 25220002 and the JST/CREST program entitled “Research and Development on Unified Environment of Accelerated Computing and Interconnection for Post-Petascale Era” in the research area of “Development of System Software Technologiesfor post-Peta Scale High Performance Computing”.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/11/27
Y1 - 2017/11/27
N2 - In most of recent Networks-on-Chip (NoCs), a simple 2D mesh structure has been adopted. However, the increasing latency caused by the large number of hops has become a problem especially in a large chip multiprocessor with increasing number of cores. Although using low ASPL networks which can reduce the hop count is a hopeful solution, a number of long wires often limits the operational frequency. Hence, we propose 3D layout of three networks: Spidergon, Flattened Butterfly, and Dragonfly on a chip stack with wireless inductive coupling through chip interface (TCI). By making the use of TCI properties, including flexible stacking and chip pass-Through data transfer, the maximum length of wires is much reduced. A large system which uses many chips can easily be implemented without degrading operational frequency.
AB - In most of recent Networks-on-Chip (NoCs), a simple 2D mesh structure has been adopted. However, the increasing latency caused by the large number of hops has become a problem especially in a large chip multiprocessor with increasing number of cores. Although using low ASPL networks which can reduce the hop count is a hopeful solution, a number of long wires often limits the operational frequency. Hence, we propose 3D layout of three networks: Spidergon, Flattened Butterfly, and Dragonfly on a chip stack with wireless inductive coupling through chip interface (TCI). By making the use of TCI properties, including flexible stacking and chip pass-Through data transfer, the maximum length of wires is much reduced. A large system which uses many chips can easily be implemented without degrading operational frequency.
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U2 - 10.1109/ISPAN-FCST-ISCC.2017.82
DO - 10.1109/ISPAN-FCST-ISCC.2017.82
M3 - Conference contribution
AN - SCOPUS:85048402241
T3 - Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017
SP - 52
EP - 59
BT - Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017
Y2 - 21 June 2017 through 23 June 2017
ER -