50% active-power saving without speed degradation using standby power reduction (SPR) circuit

Katsuhiro Seta; Hiroyuki Hara; Tadahiro Kuroda; Masakazu Kakumu; Takayasu Sakurai

50% active-power saving without speed degradation using standby power reduction (SPR) circuit

Katsuhiro Seta, Hiroyuki Hara, Tadahiro Kuroda, Masakazu Kakumu, Takayasu Sakurai

Research output: Contribution to journal › Conference article › peer-review

Abstract

To understand circuit delay and power dissipation dependence on power supply voltage (V_DD) and threshold voltage (V_TH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If V_TH is reduced to 0.3 V, V_DD can be decreased down to 2 V while maintaining the speed at V_TH = 0.7 V and V_DD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

Original language	English
Pages (from-to)	318-319
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	38
Publication status	Published - 1995 Feb 1
Externally published	Yes
Event	Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1995 Feb 15 → 1995 Feb 17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@article{59bcd0eea0e34ca89028ec71257a565d,

title = "50% active-power saving without speed degradation using standby power reduction (SPR) circuit",

abstract = "To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.",

author = "Katsuhiro Seta and Hiroyuki Hara and Tadahiro Kuroda and Masakazu Kakumu and Takayasu Sakurai",

year = "1995",

month = feb,

day = "1",

language = "English",

volume = "38",

pages = "318--319",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 IEEE International Solid-State Circuits Conference ; Conference date: 15-02-1995 Through 17-02-1995",

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TY - JOUR

T1 - 50% active-power saving without speed degradation using standby power reduction (SPR) circuit

AU - Seta, Katsuhiro

AU - Hara, Hiroyuki

AU - Kuroda, Tadahiro

AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

PY - 1995/2/1

Y1 - 1995/2/1

N2 - To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

AB - To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

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M3 - Conference article

AN - SCOPUS:0029253931

SN - 0193-6530

VL - 38

SP - 318

EP - 319

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Proceedings of the 1995 IEEE International Solid-State Circuits Conference

Y2 - 15 February 1995 through 17 February 1995

ER -

50% active-power saving without speed degradation using standby power reduction (SPR) circuit

Abstract

ASJC Scopus subject areas

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