60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinar Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama

Research output: Contribution to journalArticlepeer-review

54 Citations (Scopus)


A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-μm CMOS triple-well quad-metal technology. The videophone LSI is applied to 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm × 10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 μA, which is only 17% that for the conventional CMOS design.

Original languageEnglish
Pages (from-to)1713-1721
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number11
Publication statusPublished - 2000 Nov
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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