7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Kentaro Yoshioka; Ryo Saito; Takumi Danjo; Sanroku Tsukamoto; Hiroki Ishikuro

doi:10.1109/VLSIC.2014.6858374

7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

Original language	English
Title of host publication	2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479933273
DOIs	https://doi.org/10.1109/VLSIC.2014.6858374
Publication status	Published - 2014 Jan 1
Event	28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States Duration: 2014 Jun 10 → 2014 Jun 13

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	28th IEEE Symposium on VLSI Circuits, VLSIC 2014
Country/Territory	United States
City	Honolulu, HI
Period	14/6/10 → 14/6/13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2014.6858374

Cite this

Yoshioka, K., Saito, R., Danjo, T., Tsukamoto, S., & Ishikuro, H. (2014). 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers Article 6858374 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858374

7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. / Yoshioka, Kentaro; Saito, Ryo; Danjo, Takumi et al.
2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. 6858374 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoshioka, K, Saito, R, Danjo, T, Tsukamoto, S & Ishikuro, H 2014, 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. in 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers., 6858374, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., 28th IEEE Symposium on VLSI Circuits, VLSIC 2014, Honolulu, HI, United States, 14/6/10. https://doi.org/10.1109/VLSIC.2014.6858374

Yoshioka K, Saito R, Danjo T, Tsukamoto S, Ishikuro H. 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. 6858374. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2014.6858374

Yoshioka, Kentaro ; Saito, Ryo ; Danjo, Takumi et al. / 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.",

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AB - Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

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7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

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