7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Cool Mega Array (CMA)-SOTB-2 is an ultra-low energy Coarse Grained Reconfigurable Architecture[1] (CGRA) for recent advanced sensor networks, Internet of Things and wearable computing. It has a large Processing Element (PE) array without memory elements for mapping an application's data-flow graph, a small simple programmable μ-controller for data management, and data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. It is implemented by using Silicon on Thin BOX (SOTB) CMOS, a new process technology developed by the Low-power Electronics Association & Project (LEAP).

Original languageEnglish
Title of host publication25th International Conference on Field Programmable Logic and Applications, FPL 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9780993428005
DOIs
Publication statusPublished - 2015 Oct 7
Event25th International Conference on Field Programmable Logic and Applications, FPL 2015 - London, United Kingdom
Duration: 2015 Sept 22015 Sept 4

Other

Other25th International Conference on Field Programmable Logic and Applications, FPL 2015
Country/TerritoryUnited Kingdom
CityLondon
Period15/9/215/9/4

ASJC Scopus subject areas

  • Hardware and Architecture
  • Signal Processing
  • Software
  • Computer Science Applications

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