A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique

Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro

A 0.0058mm² 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm ² and when calibration circuit included, 0.0058 mm². With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.

Original language	English
Title of host publication	2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
Pages	C266-C267
Publication status	Published - 2013 Sept 17
Event	2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: 2013 Jun 12 → 2013 Jun 14

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2013 Symposium on VLSI Circuits, VLSIC 2013
Country/Territory	Japan
City	Kyoto
Period	13/6/12 → 13/6/14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Yoshioka, K., Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2013). A 0.0058mm² 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers (pp. C266-C267). Article 6578689 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

A 0.0058mm² 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique. / Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota et al.
2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. p. C266-C267 6578689 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoshioka, K, Shikata, A, Sekimoto, R, Kuroda, T & Ishikuro, H 2013, A 0.0058mm² 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique. in 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers., 6578689, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. C266-C267, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 13/6/12.

@inproceedings{cb0d524d3f824e24a4d1fd63e6807ce1,

title = "A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique",

abstract = "An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.",

author = "Kentaro Yoshioka and Akira Shikata and Ryota Sekimoto and Tadahiro Kuroda and Hiroki Ishikuro",

year = "2013",

month = sep,

day = "17",

language = "English",

isbn = "9784863483484",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "C266--C267",

booktitle = "2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers",

note = "2013 Symposium on VLSI Circuits, VLSIC 2013 ; Conference date: 12-06-2013 Through 14-06-2013",

}

TY - GEN

T1 - A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique

AU - Yoshioka, Kentaro

AU - Shikata, Akira

AU - Sekimoto, Ryota

AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

PY - 2013/9/17

Y1 - 2013/9/17

N2 - An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.

AB - An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.

UR - http://www.scopus.com/inward/record.url?scp=84883793033&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883793033&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84883793033

SN - 9784863483484

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C266-C267

BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers

T2 - 2013 Symposium on VLSI Circuits, VLSIC 2013

Y2 - 12 June 2013 through 14 June 2013

ER -