A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Yasuyuki Hiraku; Isamu Hayashi; Hayun Chung; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1109/IPEC.2012.6522616

A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Yasuyuki Hiraku
, Isamu Hayashi
, Hayun Chung
, Tadahiro Kuroda
, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

12 Citations (Scopus)

Abstract

This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm².

Original language	English
Pages	33-36
Number of pages	4
DOIs	https://doi.org/10.1109/IPEC.2012.6522616
Publication status	Published - 2012
Event	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan Duration: 2012 Nov 12 → 2012 Nov 14

Other

Other	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
Country/Territory	Japan
City	Kobe
Period	12/11/12 → 12/11/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/IPEC.2012.6522616

Cite this

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title = "A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS",

abstract = "This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\textbackslash{}ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2.",

author = "Yasuyuki Hiraku and Isamu Hayashi and Hayun Chung and Tadahiro Kuroda and Hiroki Ishikuro",

year = "2012",

doi = "10.1109/IPEC.2012.6522616",

language = "English",

pages = "33--36",

note = "2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 ; Conference date: 12-11-2012 Through 14-11-2012",

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T1 - A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

AU - Hiraku, Yasuyuki

AU - Hayashi, Isamu

AU - Chung, Hayun

AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

PY - 2012

Y1 - 2012

N2 - This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2.

AB - This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2.

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M3 - Paper

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T2 - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012

Y2 - 12 November 2012 through 14 November 2012

ER -

A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

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