A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    41 Citations (Scopus)

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