A 0.5V 6-bit scalable phase interpolator

Satoshi Kumaki, Abul Hasan Johari, Takeshi Matsubara, Isamu Hayashi, Hiroki Ishikuro

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    26 Citations (Scopus)


    This paper proposes a scalable phase interpolator (PI) with dual-input inverter. A pseudo-pipelined architecture is proposed to realize resolution scalability and to reduce the circuit size and power consumption. By using a simple architecture, the proposed circuit operates at 0.5V at which conventional analog PI cannot operate. Slew rate of inverter chain is controlled by current starving technique to support phase interpolation at wide input frequency range. The PI was designed in 65nm-CMOS technology. The circuit simulation confirms 6-bit phase resolution, DNL of 0.41 LSB, and INL of 1.25 LSB. The power consumption is 0.12 μW/MHz.

    Original languageEnglish
    Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
    Number of pages4
    Publication statusPublished - 2010 Dec 1
    Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
    Duration: 2010 Dec 62010 Dec 9

    Publication series

    NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS


    Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
    CityKuala Lumpur


    • DLL
    • PLL
    • multi-phase oscillator
    • phase interpolator

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering


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