A 1 TB/s 1 pJ/b 6.4 mm 2/TB/s QDR inductive-coupling interface between 65-nm CMOS logic and emulated 100-nm DRAM

Noriyuki Miura; Mitsuko Saito; Tadahiro Kuroda

doi:10.1109/JETCAS.2012.2193836

A 1 TB/s 1 pJ/b 6.4 mm ²/TB/s QDR inductive-coupling interface between 65-nm CMOS logic and emulated 100-nm DRAM

Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda

Research output: Contribution to journal › Article › peer-review

22 Citations (Scopus)

Abstract

1 TB/s 1 pJ/b 6.4 mm ²/TB/s inductive-coupling interface between 65-nm complementary metal-oxide-semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <10 ^-16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 ×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.

Original language	English
Article number	6199998
Pages (from-to)	249-256
Number of pages	8
Journal	IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Volume	2
Issue number	2
DOIs	https://doi.org/10.1109/JETCAS.2012.2193836
Publication status	Published - 2012

Keywords

High-bandwidth interface
inductive coupling
memory-processor stacking
three-dimensional integration

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/JETCAS.2012.2193836

Cite this

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title = "A 1 TB/s 1 pJ/b 6.4 mm 2/TB/s QDR inductive-coupling interface between 65-nm CMOS logic and emulated 100-nm DRAM",

abstract = "1 TB/s 1 pJ/b 6.4 mm 2/TB/s inductive-coupling interface between 65-nm complementary metal-oxide-semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <10 -16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 ×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.",

keywords = "High-bandwidth interface, inductive coupling, memory-processor stacking, three-dimensional integration",

author = "Noriyuki Miura and Mitsuko Saito and Tadahiro Kuroda",

note = "Funding Information: Manuscript received December 30, 2011; revised March 09, 2012; accepted March 24, 2012. Date of publication May 14, 2012; date of current version June 07, 2012. This work was supported by CREST/JST. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with STARC, e-Shuttle, Inc., and Fujitsu Ltd. This paper was recommended by Guest Editor K. Choi.",

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AU - Saito, Mitsuko

AU - Kuroda, Tadahiro

N1 - Funding Information: Manuscript received December 30, 2011; revised March 09, 2012; accepted March 24, 2012. Date of publication May 14, 2012; date of current version June 07, 2012. This work was supported by CREST/JST. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with STARC, e-Shuttle, Inc., and Fujitsu Ltd. This paper was recommended by Guest Editor K. Choi.

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