A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link

Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda

doi:10.1109/JSSC.2006.886554

A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link

Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

Research output: Contribution to journal › Article › peer-review

45 Citations (Scopus)

Abstract

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 μm in a layout area of 1 mm ². The total layout area including 16 clock transceivers is 2 mm ² in 0.18 μm CMOS and the chip thickness is reduced to 10 μm. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10 ^-13.

Original language	English
Pages (from-to)	111-121
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	42
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2006.886554
Publication status	Published - 2007 Jan
Externally published	Yes

Keywords

Inductor
SiP
Three-dimensional
Wireless inter-connect

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2006.886554

Cite this

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abstract = "A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 μm in a layout area of 1 mm 2. The total layout area including 16 clock transceivers is 2 mm 2 in 0.18 μm CMOS and the chip thickness is reduced to 10 μm. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10 -13.",

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author = "Noriyuki Miura and Daisuke Mizoguchi and Mari Inoue and Kiichi Niitsu and Yoshihiro Nakagawa and Masamoto Tago and Muneo Fukaishi and Takayasu Sakurai and Tadahiro Kuroda",

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AU - Miura, Noriyuki

AU - Mizoguchi, Daisuke

AU - Inoue, Mari

AU - Niitsu, Kiichi

AU - Nakagawa, Yoshihiro

AU - Tago, Masamoto

AU - Fukaishi, Muneo

AU - Sakurai, Takayasu

AU - Kuroda, Tadahiro

PY - 2007/1

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AB - A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 μm in a layout area of 1 mm 2. The total layout area including 16 clock transceivers is 2 mm 2 in 0.18 μm CMOS and the chip thickness is reduced to 10 μm. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10 -13.

KW - Inductor

KW - SiP

KW - Three-dimensional

KW - Wireless inter-connect

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A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

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