A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS

Yasumoto Tomita; Masaya Kibune; Junji Ogawa; William W. Walker; Hirotaka Tamura; Tadahiro Kuroda

doi:10.1109/JSSC.2005.845563

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS

Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda

Research output: Contribution to journal › Article › peer-review

52 Citations (Scopus)

Abstract

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-μm CMOS technology. The receiver active area is 0.8 mm² and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10^-12. The areas and power consumptions are 47 μm × 85 μzm and 13.2 mW for the equalizer, and 145 μm × 80 μm and 10 mW for the ISI monitor.

Original language	English
Pages (from-to)	986-993
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	40
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2005.845563
Publication status	Published - 2005 Apr
Externally published	Yes

Keywords

CMOS
Clock and data recovery (CDR)
Equalizer
Intersymbol interference (ISI)
Receiver

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2005.845563

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@article{478fe5b6c5f2402499601fa7a23edeb7,

title = "A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS",

abstract = "A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-μm CMOS technology. The receiver active area is 0.8 mm2 and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10-12. The areas and power consumptions are 47 μm × 85 μzm and 13.2 mW for the equalizer, and 145 μm × 80 μm and 10 mW for the ISI monitor.",

keywords = "CMOS, Clock and data recovery (CDR), Equalizer, Intersymbol interference (ISI), Receiver",

author = "Yasumoto Tomita and Masaya Kibune and Junji Ogawa and Walker, {William W.} and Hirotaka Tamura and Tadahiro Kuroda",

note = "Funding Information: Manuscript received August 26, 2004; revised January 24, 2005. This work was supported in part by a Grant in Aid for the 21st Century Center of Excellence for Optical and Electronic Device Technology for Access Network from the Ministry of Education, Culture, Sport, Science, and Technology in Japan. Y. Tomita and T. Kuroda are with the Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa 223-8522, Japan (e-mail: tomita@kuro.elec.keio.ac.jp). M. Kibune and H. Tamura are with Fujitsu Laboratories Limited, Kawasaki, Kanagawa 211-8588 Japan. J. Ogawa and W. W. Walker are with Fujitsu Laboratories of America, Sun-nyvale, CA 94085 USA. Digital Object Identifier 10.1109/JSSC.2005.845563",

year = "2005",

month = apr,

doi = "10.1109/JSSC.2005.845563",

language = "English",

volume = "40",

pages = "986--993",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS

AU - Tomita, Yasumoto

AU - Kibune, Masaya

AU - Ogawa, Junji

AU - Walker, William W.

AU - Tamura, Hirotaka

AU - Kuroda, Tadahiro

N1 - Funding Information: Manuscript received August 26, 2004; revised January 24, 2005. This work was supported in part by a Grant in Aid for the 21st Century Center of Excellence for Optical and Electronic Device Technology for Access Network from the Ministry of Education, Culture, Sport, Science, and Technology in Japan. Y. Tomita and T. Kuroda are with the Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa 223-8522, Japan (e-mail: tomita@kuro.elec.keio.ac.jp). M. Kibune and H. Tamura are with Fujitsu Laboratories Limited, Kawasaki, Kanagawa 211-8588 Japan. J. Ogawa and W. W. Walker are with Fujitsu Laboratories of America, Sun-nyvale, CA 94085 USA. Digital Object Identifier 10.1109/JSSC.2005.845563

PY - 2005/4

Y1 - 2005/4

N2 - A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-μm CMOS technology. The receiver active area is 0.8 mm2 and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10-12. The areas and power consumptions are 47 μm × 85 μzm and 13.2 mW for the equalizer, and 145 μm × 80 μm and 10 mW for the ISI monitor.

AB - A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-μm CMOS technology. The receiver active area is 0.8 mm2 and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10-12. The areas and power consumptions are 47 μm × 85 μzm and 13.2 mW for the equalizer, and 145 μm × 80 μm and 10 mW for the ISI monitor.

KW - CMOS

KW - Clock and data recovery (CDR)

KW - Equalizer

KW - Intersymbol interference (ISI)

KW - Receiver

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DO - 10.1109/JSSC.2005.845563

M3 - Article

AN - SCOPUS:18744403118

SN - 0018-9200

VL - 40

SP - 986

EP - 993

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

ER -

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS

Abstract

Keywords

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