A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications

Yosuke Toyama; Kentaro Yoshioka; Koichiro Ban; Akihide Sai; Kohei Onizuka

doi:10.1109/ASSCC.2018.8579253

A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications

Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A small gate count 8 bit bidirectional phase domain MAC (PMAC) circuit is proposed for DNN inference applications targeting IoT edge. PMAC consumes significantly smaller power than standard fully digital MACs, owing to its efficient analog accumulation nature based on Gated-Ring-Oscillator (GRO). Compared with the previous first PoC of PMAC, the bidirectional architecture proposed in this paper achieves 20% less gate count, which is comparable with fully digital MACs, and relaxes system design constraints by eliminating phase error originating in leakage current. Asynchronous readout technique and 2-step DTC for the better system throughput and compact implementation, respectively, are presented for the first time. The PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.

Original language	English
Title of host publication	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538664124
DOIs	https://doi.org/10.1109/ASSCC.2018.8579253
Publication status	Published - 2018 Dec 14
Externally published	Yes
Event	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China Duration: 2018 Nov 5 → 2018 Nov 7

Publication series

Name	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
Country/Territory	Taiwan, Province of China
City	Tainan
Period	18/11/5 → 18/11/7

Keywords

DNN accelerator
GRO
Phase Domain MAC

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2018.8579253

Cite this

Toyama, Y., Yoshioka, K., Ban, K., Sai, A., & Onizuka, K. (2018). A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings (pp. 1-4). Article 8579253 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2018.8579253

A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. / Toyama, Yosuke; Yoshioka, Kentaro; Ban, Koichiro et al.
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 8579253 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Toyama, Y, Yoshioka, K, Ban, K, Sai, A & Onizuka, K 2018, A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. in 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings., 8579253, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, Province of China, 18/11/5. https://doi.org/10.1109/ASSCC.2018.8579253

Toyama Y, Yoshioka K, Ban K, Sai A, Onizuka K. A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4. 8579253. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). doi: 10.1109/ASSCC.2018.8579253

Toyama, Yosuke ; Yoshioka, Kentaro ; Ban, Koichiro et al. / A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

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abstract = "A small gate count 8 bit bidirectional phase domain MAC (PMAC) circuit is proposed for DNN inference applications targeting IoT edge. PMAC consumes significantly smaller power than standard fully digital MACs, owing to its efficient analog accumulation nature based on Gated-Ring-Oscillator (GRO). Compared with the previous first PoC of PMAC, the bidirectional architecture proposed in this paper achieves 20% less gate count, which is comparable with fully digital MACs, and relaxes system design constraints by eliminating phase error originating in leakage current. Asynchronous readout technique and 2-step DTC for the better system throughput and compact implementation, respectively, are presented for the first time. The PMAC achieves peak efficiency of 12.4 TOPS/W in 28 nm CMOS.",

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AU - Onizuka, Kohei

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A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications

Abstract

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Keywords

ASJC Scopus subject areas

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