A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)

Daisuke Mizoguchi; Yusmeeraz Binti Yusof; Noriyuki Miura; Takayasu Sakurai; Tadahiro Kuroda

A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)

Daisuke Mizoguchi
, Yusmeeraz Binti Yusof
, Noriyuki Miura
, Takayasu Sakurai
, Tadahiro Kuroda

Research output: Contribution to journal › Conference article › peer-review

Abstract

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

Original language	English
Pages (from-to)	142-143+131+517
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	47
Publication status	Published - 2004
Event	Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States Duration: 2003 Feb 15 → 2003 Feb 19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@article{e5125302020a42a6beec693728584560,

title = "A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)",

abstract = "A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.",

author = "Daisuke Mizoguchi and Yusof, \{Yusmeeraz Binti\} and Noriyuki Miura and Takayasu Sakurai and Tadahiro Kuroda",

year = "2004",

language = "English",

volume = "47",

pages = "142--143+131+517",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference ; Conference date: 15-02-2003 Through 19-02-2003",

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T1 - A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)

AU - Mizoguchi, Daisuke

AU - Yusof, Yusmeeraz Binti

AU - Miura, Noriyuki

AU - Sakurai, Takayasu

AU - Kuroda, Tadahiro

PY - 2004

Y1 - 2004

N2 - A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

AB - A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits for non-return-to-zero signaling are developed. Test chips stacked at a distance of 300μm communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35μm CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

UR - https://www.scopus.com/pages/publications/2442653859

UR - https://www.scopus.com/pages/publications/2442653859#tab=citedBy

M3 - Conference article

AN - SCOPUS:2442653859

SN - 0193-6530

VL - 47

SP - 142-143+131+517

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference

Y2 - 15 February 2003 through 19 February 2003

ER -

A 1.2Gb/s/pin wireless superconnect based on Inductive Inter-chip Signaling (IIS)

Abstract

ASJC Scopus subject areas

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