@inproceedings{81f5df43e0e1430ea39bce388056a01c,
title = "A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration",
abstract = "A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. 'Memory effect' caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.",
keywords = "binary-search ADC, memory effect cenceller, passive pipeline operation, reference voltage calibration",
author = "Koki Tanaka and Ryo Saito and Hiroki Ishikuro",
year = "2015",
month = oct,
day = "30",
doi = "10.1109/ESSCIRC.2015.7313893",
language = "English",
series = "European Solid-State Circuits Conference",
publisher = "IEEE Computer Society",
pages = "327--330",
editor = "Franz Dielacher and Wolfgang Pribyl and Gernot Hueber",
booktitle = "ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference",
note = "41st European Solid-State Circuits Conference, ESSCIRC 2015 ; Conference date: 14-09-2015 Through 18-09-2015",
}