Abstract
A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/ m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.
| Original language | English |
|---|---|
| Pages (from-to) | 23-34 |
| Number of pages | 12 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 41 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2006 Jan |
Keywords
- 1. 2 W
- 195 Gbit/s
- 3D stacked system in a package
- 50 micron
- CMOS technology
- Crosstalk
- Inductive coupling
- Inductive interchip wireless superconnect
- Low power single end transmitter
- Power dissipation
- Transmit power control scheme
- Wireless interconnect
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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