TY - GEN
T1 - A 1Tb/s 3W inductive-coupling transceiver chip
AU - Miura, Noriyuki
AU - Kuroda, Tadahiro
PY - 2007/12/1
Y1 - 2007/12/1
N2 - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm 2. The total layout area including 16 clock transceivers is 2mm 2 in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 -13 with 150ps timing margin.
AB - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm 2. The total layout area including 16 clock transceivers is 2mm 2 in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 -13 with 150ps timing margin.
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U2 - 10.1109/ASPDAC.2007.357798
DO - 10.1109/ASPDAC.2007.357798
M3 - Conference contribution
AN - SCOPUS:46649099879
SN - 1424406293
SN - 9781424406296
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 92
EP - 93
BT - Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
T2 - ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Y2 - 23 January 2007 through 27 January 2007
ER -