A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

88 Citations (Scopus)

Abstract

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm² in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10^-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.

Original language	English
Title of host publication	2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages	424+417
Publication status	Published - 2006
Event	2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2006 Feb 6 → 2006 Feb 9

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	2006 IEEE International Solid-State Circuits Conference, ISSCC
Country/Territory	United States
City	San Francisco, CA
Period	06/2/6 → 06/2/9

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Miura, N., Mizoguchi, D., Inoue, M., Niitsu, K., Nakagawa, Y., Tago, M., Fukaishi, M., Sakurai, T., & Kuroda, T. (2006). A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. In 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 424+417). Article 1696223 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. / Miura, Noriyuki; Mizoguchi, Daisuke; Inoue, Mari et al.
2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. 2006. p. 424+417 1696223 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Miura, N, Mizoguchi, D, Inoue, M, Niitsu, K, Nakagawa, Y, Tago, M, Fukaishi, M, Sakurai, T & Kuroda, T 2006, A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. in 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 1696223, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp. 424+417, 2006 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 06/2/6.

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AU - Tago, Masamoto

AU - Fukaishi, Muneo

AU - Sakurai, Takayasu

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AB - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.

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BT - 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers

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A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

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