A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking

Noriyuki Miura; Yasuhiro Take; Mitsuko Saito; Yoichi Yoshida; Tadahiro Kuroda

doi:10.1109/ISSCC.2011.5746410

A 2.7Gb/s/mm² 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking

Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

This paper presents an inductive-coupling interface for NAND Flash memory stacking whose bandwidth per unit area is 2.7Gb/s/mm² and energy consumption per chip is 0.9pJ/b/chip. The bandwidth is increased by 10x (in other words, layout area is reduced to 1/10 for the same data rate), and the energy consumption is reduced by half, both compared to the latest research results [1]. A relayed transmission scheme using one coil is proposed to reduce the number of coils in a data link. Coupled resonation is utilized for clock and data recovery (CDR) for the first time in the world, resulting in elimination of a source synchronous clock link. As a result, total number of coils needed to form a channel is reduced from 6 to 1, yielding the significant improvement in data rate, layout area and energy consumption.

Original language	English
Title of host publication	2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	490-491
Number of pages	2
ISBN (Print)	9781612843001
DOIs	https://doi.org/10.1109/ISSCC.2011.5746410
Publication status	Published - 2011
Externally published	Yes
Event	2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States Duration: 2011 Feb 20 → 2011 Feb 24

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Country/Territory	United States
City	San Francisco, CA
Period	11/2/20 → 11/2/24

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISSCC.2011.5746410

Cite this

Miura, N., Take, Y., Saito, M., Yoshida, Y., & Kuroda, T. (2011). A 2.7Gb/s/mm² 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011 (pp. 490-491). Article 5746410 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2011.5746410

A 2.7Gb/s/mm² 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. / Miura, Noriyuki; Take, Yasuhiro; Saito, Mitsuko et al.
2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. p. 490-491 5746410 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Miura, N, Take, Y, Saito, M, Yoshida, Y & Kuroda, T 2011, A 2.7Gb/s/mm² 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. in 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011., 5746410, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 490-491, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, CA, United States, 11/2/20. https://doi.org/10.1109/ISSCC.2011.5746410

Miura N, Take Y, Saito M, Yoshida Y, Kuroda T. A 2.7Gb/s/mm² 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc. 2011. p. 490-491. 5746410. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2011.5746410

Miura, Noriyuki ; Take, Yasuhiro ; Saito, Mitsuko et al. / A 2.7Gb/s/mm² 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND flash memory stacking. 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. pp. 490-491 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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