TY - JOUR
T1 - A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique
AU - Okaniwa, Yusuke
AU - Tamura, Hirotaka
AU - Kibune, Masaya
AU - Yamazaki, Daisuke
AU - Cheung, Tsz Shing
AU - Ogawa, Junji
AU - Tzartzanis, Nestoras
AU - Walker, William W.
AU - Kuroda, Tadahiro
N1 - Funding Information:
Manuscript received September 18, 2004; revised May 2, 2005. This work was supported in part by a Grant in Aid for the 21st Century Center of Excellence for Optical and Electronic Device Technology for Access Network from the Ministry of Education, Culture, Sport, Science, and Technology in Japan. Y. Okaniwa and T. Kuroda are with the Department of Electronics and Electrical Engineering, Keio University, Kanagawa 223-8522, Japan (e-mail: okaniwa@kuro.elec.keio.ac.jp). H. Tamura, M. Kibune, D. Yamazaki, T.-S. Cheung, and J. Ogawa are with the Fujitsu Laboratories Ltd., Kanagawa 223-8522, Kawasaki, Japan. N. Tzartzanis and W. W. Walker are with the Fujitsu Laboratories of America, Inc., Sunnyvale, CA 94085 USA. Digital Object Identifier 10.1109/JSSC.2005.852014
PY - 2005/8
Y1 - 2005/8
N2 - A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-μm standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10 -12 by laboratory measurements.
AB - A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-μm standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10 -12 by laboratory measurements.
KW - CMOS integrated circuits
KW - Comparators
KW - High-speed integrated circuits
UR - http://www.scopus.com/inward/record.url?scp=23744451801&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=23744451801&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2005.852014
DO - 10.1109/JSSC.2005.852014
M3 - Article
AN - SCOPUS:23744451801
SN - 0018-9200
VL - 40
SP - 1680
EP - 1686
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 8
ER -