A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

Ryota Sekimoto; Akira Shikata; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1109/ESSCIRC.2011.6045009

A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Citations (Scopus)

Abstract

This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB.

Original language	English
Title of host publication	ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages	471-474
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2011.6045009
Publication status	Published - 2011
Event	37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland Duration: 2011 Sept 12 → 2011 Sept 16

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Other

Other	37th European Solid-State Circuits Conference, ESSCIRC 2011
Country/Territory	Finland
City	Helsinki
Period	11/9/12 → 11/9/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2011.6045009

Cite this

A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. / Sekimoto, Ryota; Shikata, Akira; Kuroda, Tadahiro et al.
ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. 2011. p. 471-474 6045009 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sekimoto, R, Shikata, A, Kuroda, T & Ishikuro, H 2011, A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. in ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference., 6045009, European Solid-State Circuits Conference, pp. 471-474, 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, 11/9/12. https://doi.org/10.1109/ESSCIRC.2011.6045009

@inproceedings{824d0d8722714d4886d2e08275a1cc27,

title = "A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator",

abstract = "This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB.",

author = "Ryota Sekimoto and Akira Shikata and Tadahiro Kuroda and Hiroki Ishikuro",

year = "2011",

doi = "10.1109/ESSCIRC.2011.6045009",

language = "English",

isbn = "9781457707018",

series = "European Solid-State Circuits Conference",

pages = "471--474",

booktitle = "ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference",

note = "37th European Solid-State Circuits Conference, ESSCIRC 2011 ; Conference date: 12-09-2011 Through 16-09-2011",

}

TY - GEN

T1 - A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

AU - Sekimoto, Ryota

AU - Shikata, Akira

AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

PY - 2011

Y1 - 2011

N2 - This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB.

AB - This paper presents an ultra low power and low voltage successive- approximation-register (SAR) analog-to-digital converter (ADC) that uses an adaptive timing optimized asynchronous clock generator. Compared to asynchronous converters that use the conventional clock generator, the frequency range is expanded by 50% at 0.4V analog and 0.7V digital power supply voltage. By calibrating the delay time of the clock generator, the DAC settling time is optimized to counter the device mismatch. Test chip has been fabricated in 40nm standard CMOS process and achieved figure of merit (FoM) of 8.75-fJ/conversion- step with 2.048MS/s at 0.6V analog and 0.7V digital power supply voltage. The ADC operates from 50S/s to 8MS/s performing over 7.5-ENOB.

UR - http://www.scopus.com/inward/record.url?scp=82955164353&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=82955164353&partnerID=8YFLogxK

U2 - 10.1109/ESSCIRC.2011.6045009

DO - 10.1109/ESSCIRC.2011.6045009

M3 - Conference contribution

AN - SCOPUS:82955164353

SN - 9781457707018

T3 - European Solid-State Circuits Conference

SP - 471

EP - 474

BT - ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference

T2 - 37th European Solid-State Circuits Conference, ESSCIRC 2011

Y2 - 12 September 2011 through 16 September 2011

ER -

A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

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