A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration

Kaoru Yamashita, Benjamin Hershberg, Kentaro Yoshioka, Hiroki Ishikuro

Research output: Contribution to journalArticlepeer-review

Abstract

This article presents a process voltage temperature (PVT) -robust ring amplifier that enables a high speed pipelined analog-to-digital-converter (ADC) without gain calibration, operating across a temperature range of 4.6-400 K. To ensure the stability of the ringamp, given the large variation of MOSFET transconductance, threshold voltage, and drain resistance across temperature, we propose a unity-gain-frequency-aware bias calibration and a 1st-stage bias-enhancement technique. The unity-gain-frequency-aware bias calibration stabilizes the amplifier bandwidth by biasing the 3rd stage of the ringamp using a constant-Gm circuit and then optimizing the overall phase margin by tuning the 1st and 2nd stages based on feedback from an amplifier output settling monitor. An additional bias-enhancement technique alleviates the issue of insufficient voltage headroom at cryogenic temperatures (CTs) in the fully differential first stage of the ringamp. This is achieved by separately ac-coupling the NMOS and PMOS of the 1st-stage inverter. Furthermore, to deal with insufficient gain in advanced CMOS process, a cascode correlated-level-shifting (CLS) technique is proposed. This enables gain-calibration-free operation while achieving higher speed than conventional CLS. A 12-bit 250 MS/s pipelined ADC prototype is fabricated with the proposed ringamp in 65 nm CMOS technology. It achieves a signal to noise and distortion ratio (SNDR) above 57.7 dB across the 4.6-400 K temperature range, and Walden figure-of-merit (FoM) of 154 fJ/conv.-step at 4.6 K while operating without any gain calibrations. To the best of our knowledge, the achieved functional temperature range is the widest ever reported for a pipelined ADC.

Original languageEnglish
Pages (from-to)740-752
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume59
Issue number3
DOIs
Publication statusPublished - 2024 Mar 1

Keywords

  • 4 K
  • analog-to-digital (A/D)
  • analog-to-digital conversion
  • analog-to-digital-converter (ADC)
  • cascode correlated level shifting (CLS)
  • cryo-CMOS
  • cryogenic
  • data converter
  • pipeline
  • pipelined ADC
  • ring amplifier
  • ringamp

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration'. Together they form a unique fingerprint.

Cite this