A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

Xiaolei Zhu; Yanfei Chen; Sanroku Tsukamoto; Tadahiro Kuroda

doi:10.1109/VLSI-DAT.2012.6212592

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/0.5 LSB DNL and +0.5/0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.10.13 mm ².

Original language	English
Title of host publication	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-DAT.2012.6212592
Publication status	Published - 2012
Event	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan, Province of China Duration: 2012 Apr 23 → 2012 Apr 25

Publication series

Name	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Other

Other	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	12/4/23 → 12/4/25

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1109/VLSI-DAT.2012.6212592

Cite this

Zhu, X., Chen, Y., Tsukamoto, S., & Kuroda, T. (2012). A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers Article 6212592 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212592

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. / Zhu, Xiaolei; Chen, Yanfei; Tsukamoto, Sanroku et al.
2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212592 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhu, X, Chen, Y, Tsukamoto, S & Kuroda, T 2012, A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. in 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212592, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, Province of China, 12/4/23. https://doi.org/10.1109/VLSI-DAT.2012.6212592

Zhu X, Chen Y, Tsukamoto S, Kuroda T. A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212592. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). doi: 10.1109/VLSI-DAT.2012.6212592

Zhu, Xiaolei ; Chen, Yanfei ; Tsukamoto, Sanroku et al. / A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

@inproceedings{146993d093194e80ad68c321b2999ece,

title = "A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array",

abstract = "The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/0.5 LSB DNL and +0.5/0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.10.13 mm 2.",

author = "Xiaolei Zhu and Yanfei Chen and Sanroku Tsukamoto and Tadahiro Kuroda",

year = "2012",

doi = "10.1109/VLSI-DAT.2012.6212592",

language = "English",

isbn = "9781457720819",

series = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

booktitle = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

note = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 ; Conference date: 23-04-2012 Through 25-04-2012",

}

TY - GEN

T1 - A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

AU - Zhu, Xiaolei

AU - Chen, Yanfei

AU - Tsukamoto, Sanroku

AU - Kuroda, Tadahiro

PY - 2012

Y1 - 2012

N2 - The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/0.5 LSB DNL and +0.5/0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.10.13 mm 2.

AB - The capacitor digital-to-analog converter (CDAC) which affects the system performance of speed and linearity occupies the most area in successive approximation register (SAR) analog-to-digital converter (ADC). The performance of tri-level SAR ADC is well balanced between power and speed comparing to the conventional CDAC based architecture. In order to further improve the ADC performance in light of area and energy efficiencies, a partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well. Combining the asymmetric CDAC approach with the tri-level charge redistribution technique makes it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays. A 9-bit SAR ADC with CDAC calibration has been implemented in a 65nm CMOS technology and it achieves a peak SNDR of 50.1 dB and consumes 1.26 mW from a 1.2-V supply, corresponding to a FOM of 45fJ/conv.-step. The static performance of +0.4/0.5 LSB DNL and +0.5/0.7 LSB INL is achieved. The ADC has input capacitance of 180 fF and occupies an active area of 0.10.13 mm 2.

UR - http://www.scopus.com/inward/record.url?scp=84864047358&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84864047358&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2012.6212592

DO - 10.1109/VLSI-DAT.2012.6212592

M3 - Conference contribution

AN - SCOPUS:84864047358

SN - 9781457720819

T3 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

BT - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

T2 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012

Y2 - 23 April 2012 through 25 April 2012

ER -

A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this