A Compression Router for Low-Latency Network-on-Chip

Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi

Research output: Contribution to journalArticlepeer-review


Network-on-Chips (NoCs) are important components for scalable many-core processors. Because the performance of parallel applications is usually sensitive to the latency of NoCs, reducing it is a primary requirement. In this study, a compression router that hides the (de)compression-operation delay is proposed. The compression router (de)compresses the contents of the incoming packet before the switch arbitration is completed, thus shortening the packet length without latency penalty and reducing the network injection-and-ejection latency. Evaluation results show that the compression router improves up to 33% of the parallel application performance (conjugate gradients (CG), fast Fourier transform (FT), integer sort (IS), and traveling salesman problem (TSP)) and 63% of the effective network throughput by 1.8 compression ratio on NoC. The cost is an increase in router area and its energy consumption by 0.22mm2 and 1.6 times compared to the conventional virtual-channel router. Another finding is that off-loading the decompressor onto a network interface decreases the compression-router area by 57% at the expense of the moderate increase in communication latency.

Original languageEnglish
Pages (from-to)170-180
Number of pages11
JournalIEICE Transactions on Information and Systems
Issue number2
Publication statusPublished - 2023 Feb


  • lossy data compression
  • Network-on-Chips
  • router architecture

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


Dive into the research topics of 'A Compression Router for Low-Latency Network-on-Chip'. Together they form a unique fingerprint.

Cite this