A high speed license plate recognition system on an FPGA

Takamasa Kanamori; Hideharu Amano; Masatoshi Arai; Daisuke Konno; Tomomichi Nanba; Yoshiaki Ajioka

doi:10.1109/FPL.2007.4380715

A high speed license plate recognition system on an FPGA

Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A pro-totype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-Ill desktop PC. The highest performance in literature; 100 frames per second; can be achieved.

Original language	English
Title of host publication	Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
Pages	554-557
Number of pages	4
DOIs	https://doi.org/10.1109/FPL.2007.4380715
Publication status	Published - 2007
Event	2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands Duration: 2007 Aug 27 → 2007 Aug 29

Publication series

Name	Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Other

Other	2007 International Conference on Field Programmable Logic and Applications, FPL
Country/Territory	Netherlands
City	Amsterdam
Period	07/8/27 → 07/8/29

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/FPL.2007.4380715

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Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T., & Ajioka, Y. (2007). A high speed license plate recognition system on an FPGA. In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL (pp. 554-557). Article 4380715 (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL). https://doi.org/10.1109/FPL.2007.4380715

A high speed license plate recognition system on an FPGA. / Kanamori, Takamasa; Amano, Hideharu; Arai, Masatoshi et al.
Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. p. 554-557 4380715 (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kanamori, T, Amano, H, Arai, M, Konno, D, Nanba, T & Ajioka, Y 2007, A high speed license plate recognition system on an FPGA. in Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL., 4380715, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL, pp. 554-557, 2007 International Conference on Field Programmable Logic and Applications, FPL, Amsterdam, Netherlands, 07/8/27. https://doi.org/10.1109/FPL.2007.4380715

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A high speed license plate recognition system on an FPGA

Abstract

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Other

ASJC Scopus subject areas

UN SDGs

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