TY - GEN
T1 - A local area system network RHiNET-1
T2 - 9th IEEE International Symposium on High-Performance Distributed Computing, HPDC 2000
AU - Nishi, H.
AU - Tasho, K.
AU - Yamamoto, J.
AU - Kudoh, T.
AU - Amano, H.
N1 - Publisher Copyright:
© 2000 IEEE.
PY - 2000
Y1 - 2000
N2 - The Real World Computing Partnership (RWCP) has developed a local area system network (LASN) called RHiNET-1 (RWCP High-performance NETwork, version 1) using 1.33-Gbps optical interconnections for high-performance computing using personal computers distributed in an office or laboratory environment. The network interface, RHiNET-1/NI, uses a complex programmable logic device (CPLD) based protocol controller to provide an easy evaluation platform for various protocols. It fits in a 32-bit/33-MHz PCI bus. The switch, RHiNET-1/SW, consists of a single-chip CMOS switch and external SRAM. It provides low-latency, reliable communication with a flexible topology design. We are currently evaluating protocols on RHiNET-1. RHiNET-1 will enable a new form of high-performance computing environment. We are also developing the second implementation, RHiNET-2. RHiNET-2/NI will support a 64-bit/66-MHz PCI bus. RHiNET-2/SW is an 8-Gbps/port 8x8 single-chip ASIC switch. The aggregate bandwidth of RHiNET-2/SW is 64 Gbps.
AB - The Real World Computing Partnership (RWCP) has developed a local area system network (LASN) called RHiNET-1 (RWCP High-performance NETwork, version 1) using 1.33-Gbps optical interconnections for high-performance computing using personal computers distributed in an office or laboratory environment. The network interface, RHiNET-1/NI, uses a complex programmable logic device (CPLD) based protocol controller to provide an easy evaluation platform for various protocols. It fits in a 32-bit/33-MHz PCI bus. The switch, RHiNET-1/SW, consists of a single-chip CMOS switch and external SRAM. It provides low-latency, reliable communication with a flexible topology design. We are currently evaluating protocols on RHiNET-1. RHiNET-1 will enable a new form of high-performance computing environment. We are also developing the second implementation, RHiNET-2. RHiNET-2/NI will support a 64-bit/66-MHz PCI bus. RHiNET-2/SW is an 8-Gbps/port 8x8 single-chip ASIC switch. The aggregate bandwidth of RHiNET-2/SW is 64 Gbps.
KW - Communication switching
KW - Computer networks
KW - Distributed computing
KW - Microcomputers
KW - Network interfaces
KW - Optical computing
KW - Optical interconnections
KW - Programmable logic devices
KW - Protocols
KW - Switches
UR - http://www.scopus.com/inward/record.url?scp=0033699045&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033699045&partnerID=8YFLogxK
U2 - 10.1109/HPDC.2000.868665
DO - 10.1109/HPDC.2000.868665
M3 - Conference contribution
AN - SCOPUS:0033699045
T3 - Proceedings of the IEEE International Symposium on High Performance Distributed Computing
SP - 296
EP - 297
BT - Proceedings - The 9th International Symposium on High-Performance Distributed Computing, HPDC 2000
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 1 August 2000 through 4 August 2000
ER -