TY - GEN
T1 - A low-power multi-frequency chopper-stabilized readout with time-domain delta-sigma modulator suitable for neural recording
AU - Mikawa, Mikiyoshi
AU - Yagi, Kenta
AU - Itakura, Kazuki
AU - Onuki, Leo
AU - Nakano, Nobuhiko
N1 - Funding Information:
ACKNOWLEDGMENT This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/11/23
Y1 - 2020/11/23
N2 - This paper presents a readout for multi-channel neural recording. The proposed architecture is implemented with a system-level frequency-division multiplexing technique and a time-domain delta-sigma modulator. Subthreshold region operation and the time-domain delta-sigma modulator achieves a reduction of the current dissipation. The multiplexing technique in the frequency domain enhances the power efficiency by sharing an instrumentation amplifier and the delta-sigma modulator in each channel. The proposed circuit employs a pulse-width summation technique to achieve frequency-division multiplexing in the time-domain delta-sigma modulator. The multiplexing technique of multiple frequency chopper stabilization can eliminate flicker noise and offsets. The proposed two-channel readout occupies 0.067 mm2 per channel and is designed with 0.18-µm CMOS technology. The spurious-free dynamic range is up to 50 dB in a bandwidth of 625 Hz with a low power consumption of 520 nW per channel.
AB - This paper presents a readout for multi-channel neural recording. The proposed architecture is implemented with a system-level frequency-division multiplexing technique and a time-domain delta-sigma modulator. Subthreshold region operation and the time-domain delta-sigma modulator achieves a reduction of the current dissipation. The multiplexing technique in the frequency domain enhances the power efficiency by sharing an instrumentation amplifier and the delta-sigma modulator in each channel. The proposed circuit employs a pulse-width summation technique to achieve frequency-division multiplexing in the time-domain delta-sigma modulator. The multiplexing technique of multiple frequency chopper stabilization can eliminate flicker noise and offsets. The proposed two-channel readout occupies 0.067 mm2 per channel and is designed with 0.18-µm CMOS technology. The spurious-free dynamic range is up to 50 dB in a bandwidth of 625 Hz with a low power consumption of 520 nW per channel.
KW - Electroencephalogram (EEG)
KW - Gated ring oscillator (GRO)
KW - Multi-channel recording
KW - Multi-frequency chopping
KW - Subthreshold region operation
KW - Time-to-digital converter (TDC)
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U2 - 10.1109/ICECS49266.2020.9294871
DO - 10.1109/ICECS49266.2020.9294871
M3 - Conference contribution
AN - SCOPUS:85099477194
T3 - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
BT - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020
Y2 - 23 November 2020 through 25 November 2020
ER -