TY - GEN
T1 - A preliminarily evaluation of PEACH3
T2 - 2nd International Symposium on Computing and Networking, CANDAR 2014
AU - Kuhara, Takuya
AU - Kaneda, Takahiro
AU - Hanawa, Toshihiro
AU - Kodama, Yuetsu
AU - Boku, Taisuke
AU - Amano, Hideharu
PY - 2015/2/27
Y1 - 2015/2/27
N2 - Tightly coupled accelerators (TCA) architecture consists of heterogeneous nodes connected to a low-latency high-bandwidth network which allows accelerators to communicate directly. PCI express adaptive communication hub (PEACH) is a switch that connects multiple nodes with the PCIe to build a ring based network in which PCIe packets are directly forwarded. PEACH2, the current version of PEACH uses Altera's field programmable gate array (FPGA) Stratix IV GX and provides four PCIe Gen2 x 8 ports to form a stand-alone network. We developed PEACH3, an advanced version of PEACH2 and its preliminary evaluation result is shown. In PEACH3, the PCIe Gen2 was changed to Gen3 and the internal bus was extended from 128 to 256 bits. PEACH3 is implemented with Altera's Stratix V FPGA which works using a 250MHz clock, and provides four PCIe Gen3 x 8 ports. Stable communication between two nodes through two PCIe Gen3 connected PEACH3 boards was achieved, and communication bandwidth between two nodes was up to 6.9GB/sec, about 87% maximum performance of PCI Gen3 specification.
AB - Tightly coupled accelerators (TCA) architecture consists of heterogeneous nodes connected to a low-latency high-bandwidth network which allows accelerators to communicate directly. PCI express adaptive communication hub (PEACH) is a switch that connects multiple nodes with the PCIe to build a ring based network in which PCIe packets are directly forwarded. PEACH2, the current version of PEACH uses Altera's field programmable gate array (FPGA) Stratix IV GX and provides four PCIe Gen2 x 8 ports to form a stand-alone network. We developed PEACH3, an advanced version of PEACH2 and its preliminary evaluation result is shown. In PEACH3, the PCIe Gen2 was changed to Gen3 and the internal bus was extended from 128 to 256 bits. PEACH3 is implemented with Altera's Stratix V FPGA which works using a 250MHz clock, and provides four PCIe Gen3 x 8 ports. Stable communication between two nodes through two PCIe Gen3 connected PEACH3 boards was achieved, and communication bandwidth between two nodes was up to 6.9GB/sec, about 87% maximum performance of PCI Gen3 specification.
KW - Accelerators
KW - FPGA
KW - High speed switching hub
KW - PCIe gen3
UR - http://www.scopus.com/inward/record.url?scp=84925400348&partnerID=8YFLogxK
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U2 - 10.1109/CANDAR.2014.44
DO - 10.1109/CANDAR.2014.44
M3 - Conference contribution
AN - SCOPUS:84925400348
T3 - Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014
SP - 377
EP - 381
BT - Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 10 December 2014 through 12 December 2014
ER -