A resource-efficient design for a reversible floating point adder in quantum computing

Trung Duc Nguyen, Rodney Van Meter

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)


Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this article, we propose a resource-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. [2011]. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost by about 68%. We also propose quantum designs adapted to use gates from fault-tolerant libraries. The KQ for our fault-tolerant design is almost 60 times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.

Original languageEnglish
Article numberA13
JournalACM Journal on Emerging Technologies in Computing Systems
Issue number2
Publication statusPublished - 2014 Oct 1


  • Floating-point arithmetic
  • IEEE-754 specification
  • Low-power computing
  • Nano technology
  • Quantum computing
  • Reversible circuit

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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