A study of adaptable co-processors for cyclic redundancy check on an FPGA

Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect corruption of digital content in digital networks and storage devices. In this paper, we present a study of different approaches of designing highly adaptable co-processors for CRC on an FPGA which are used in many network and server applications. The results of our research are two new architectures: adaptable and dynamically re-configurable CRC co-processors. Both architectures are highly flexible in terms of a number of CRC standards they support. We explored their scalability by processing different amount of input messages at a time. Results show that throughput doubles when we double the amount of data processed at a time. Our experimental results on adaptable CRC co-processor demonstrate re-generation latency as low as.9 - 4.52μs and throughput between 27.8 - 418Gbps (64 - 1024 bits of an input message). The re-configuration latency of dynamic parts of other CRC co-processor was significantly higher.3 -.45s, but area utilization was the least. The throughput of this architecture was between 29.25 - 347.37 Gbps.