A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

Masaru Kato; Toru Sano; Yoshihiro Yasuda; Yoshiki Saito; Hideharu Amano

doi:10.1109/FPT.2009.5377694

A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

Masaru Kato, Toru Sano, Yoshihiro Yasuda, Yoshiki Saito, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A Dynamically Reconfigurable Processor Array (DRPA) is consisting of a number of PEs, and its interconnection of PE array gives a large effect on the total area, energy and performance. However, there is no study of DRPAs focused on their PE network. In this paper, we designed four types of DRPAs based on MuCCRA, developed in MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project. They have different topologies, which are direct interconnection, island-style interconnection and two kinds of hybrid interconnection. They are evaluated using three different PE array sizes. As a result, a MuCCRA with hybrid network, which has the highest degree of connectivity, is able to execute DCT faster than the other MuCCRAs, but requires more area by 20% than MuCCRA with direct network. On energy consumption, MuCCRA with direct links consumes 7 times more energy at maximum than island-style-interconnected MuCCRAs.

Original language	English
Title of host publication	Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09
Pages	415-418
Number of pages	4
DOIs	https://doi.org/10.1109/FPT.2009.5377694
Publication status	Published - 2009 Dec 1
Event	2009 International Conference on Field-Programmable Technology, FPT'09 - Sydney, Australia Duration: 2009 Dec 9 → 2009 Dec 11

Publication series

Name	Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Other

Other	2009 International Conference on Field-Programmable Technology, FPT'09
Country/Territory	Australia
City	Sydney
Period	09/12/9 → 09/12/11

ASJC Scopus subject areas

Computational Theory and Mathematics
Hardware and Architecture
Software

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/FPT.2009.5377694

Cite this

Kato, M., Sano, T., Yasuda, Y., Saito, Y., & Amano, H. (2009). A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA. In Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09 (pp. 415-418). Article 5377694 (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09). https://doi.org/10.1109/FPT.2009.5377694

A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA. / Kato, Masaru; Sano, Toru; Yasuda, Yoshihiro et al.
Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. 2009. p. 415-418 5377694 (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kato, M, Sano, T, Yasuda, Y, Saito, Y & Amano, H 2009, A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA. in Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09., 5377694, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09, pp. 415-418, 2009 International Conference on Field-Programmable Technology, FPT'09, Sydney, Australia, 09/12/9. https://doi.org/10.1109/FPT.2009.5377694

Kato M, Sano T, Yasuda Y, Saito Y, Amano H. A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA. In Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. 2009. p. 415-418. 5377694. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09). doi: 10.1109/FPT.2009.5377694

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abstract = "A Dynamically Reconfigurable Processor Array (DRPA) is consisting of a number of PEs, and its interconnection of PE array gives a large effect on the total area, energy and performance. However, there is no study of DRPAs focused on their PE network. In this paper, we designed four types of DRPAs based on MuCCRA, developed in MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project. They have different topologies, which are direct interconnection, island-style interconnection and two kinds of hybrid interconnection. They are evaluated using three different PE array sizes. As a result, a MuCCRA with hybrid network, which has the highest degree of connectivity, is able to execute DCT faster than the other MuCCRAs, but requires more area by 20% than MuCCRA with direct network. On energy consumption, MuCCRA with direct links consumes 7 times more energy at maximum than island-style-interconnected MuCCRAs.",

author = "Masaru Kato and Toru Sano and Yoshihiro Yasuda and Yoshiki Saito and Hideharu Amano",

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A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

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ASJC Scopus subject areas

UN SDGs

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