Adaptive data compression on 3D network-on-chips

Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


The three-dimensional Network-on-Chip (3D NoC) is an emerging research topic exploring the network architecture of 3D ICs that stack several wafers or dies. As such topics being extensively studied, it is found negative impacts of 3D NoC's vertical interconnects are raising concerns considering their footprint sizes and routability degradation. In our evaluation, we found such vertical bandwidth limitation can dramatically degrade system performance by up to 2.3×. Since such limitations come from physical design constraints, to mitigate performance degradation, we have no other choice but to reduce the amount of communication data on-chip, especially for those data moving vertically. In this paper, therefore, we carry out a study of data compression on 3D NoC architectures with a comprehensive set of scientific workloads. Firstly, we propose an adaptive data compression scheme for 3D NoCs, taking account of the vertical bandwidth limitation and data compressibility. Secondly, we evaluate our proposal on a 3D NoC platform and we observe that the compressibility based adaptive compression is very useful against incompressible data while the location-based adaptive compression is more effective with more layers for the 3D NoC. Thirdly, we find that in a bandwidth limited situation like a CMP with 3D NoCs having multiple connected layers, adaptive data compression with location-based control or with both compressibility and location based control is very promising if the number of layers grows.

Original languageEnglish
Pages (from-to)13-20
Number of pages8
JournalIPSJ Online Transactions
Issue number1
Publication statusPublished - 2012
Externally publishedYes


  • 3D Network-on-chip
  • Chip-multi processor
  • Data compression

ASJC Scopus subject areas

  • General Computer Science


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