An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept

Peter Toth; Hiroki Ishikuro

doi:10.1145/3394885.3431643

An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept

Peter Toth, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents a wide-dynamic-range high-resolution timedomain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept allows a virtual delay line extension and is applied to achieve high resolution down to 1ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1ns to 12 ns allow on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. The concept of this paper is evaluated by a custom-designed FPGA supported PCB. The presented concept is highly suitable for onchip integration.

Original language	English
Title of host publication	Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	105-106
Number of pages	2
ISBN (Electronic)	9781450379991
DOIs	https://doi.org/10.1145/3394885.3431643
Publication status	Published - 2021 Jan 18
Event	26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan Duration: 2021 Jan 18 → 2021 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
Country/Territory	Japan
City	Virtual, Online
Period	21/1/18 → 21/1/21

Keywords

Low-Power TDC
Multi-Stage TDC
Sensor Interface
Time-Domain Converter (TDC)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1145/3394885.3431643

Cite this

Toth, P., & Ishikuro, H. (2021). An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 (pp. 105-106). Article 3431643 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3394885.3431643

An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. / Toth, Peter; Ishikuro, Hiroki.
Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 105-106 3431643 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Toth, P & Ishikuro, H 2021, An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. in Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021., 3431643, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 105-106, 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021, Virtual, Online, Japan, 21/1/18. https://doi.org/10.1145/3394885.3431643

Toth P, Ishikuro H. An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 105-106. 3431643. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/3394885.3431643

Toth, Peter ; Ishikuro, Hiroki. / An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept. Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. pp. 105-106 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

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abstract = "This paper presents a wide-dynamic-range high-resolution timedomain converter concept tailored for low-power sensor interfaces. The unique system structure applies different techniques to reduce circuit complexity, power consumption, and noise sensitivity. A multi-cycle concept allows a virtual delay line extension and is applied to achieve high resolution down to 1ns. At the same time, it expands the dynamic range drastically up to 2.35 ms. Moreover, individually tunable delay elements in the range of 1ns to 12 ns allow on-demand flexible operation in a low- or high-resolution mode for smart sensing applications and flexible power control. The concept of this paper is evaluated by a custom-designed FPGA supported PCB. The presented concept is highly suitable for onchip integration.",

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An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this