An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings

Ayaka Ohwada, Takuya Kojima, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In recent years, IoT devices have become widespread, and energy-efficient coarse-grained reconfigurable architectures (CGRAs) have attracted attention. CGRAs comprise several processing units called processing elements (PEs) arranged in a two-dimensional array. The operations of PEs and the interconnections between them are adaptively changed depending on a target application, and this contributes to a higher energy efficiency compared to general-purpose processors. The application kernel executed on CGRAs is represented as a data flow graph (DFG), and CGRA compilers are responsible for mapping the DFG onto the PE array. Thus, mapping algorithms significantly influence the performance and power efficiency of CGRAs as well as the compile time. This paper proposes POCOCO, a compiler framework for CGRAs that can use pre-optimized subgraph mappings. This contributes to reducing the compiler optimization task. To leverage the subgraph mappings, we extend an existing mapping method based on a genetic algorithm. Experiments on three architectures demonstrated that the proposed method reduces the optimization time by 48%, on an average, for the best case of the three architectures.

Original languageEnglish
Title of host publicationProceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022
EditorsArturo Gonzalez-Escribano, Jose Daniel Garcia, Massimo Torquati, Amund Skavhaug
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-9
Number of pages9
ISBN (Electronic)9781665469586
DOIs
Publication statusPublished - 2022
Event30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022 - Valladolid, Spain
Duration: 2022 Mar 92022 Mar 11

Publication series

NameProceedings - 30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022

Conference

Conference30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2022
Country/TerritorySpain
CityValladolid
Period22/3/922/3/11

Keywords

  • coarse grained reconfigurable architectures
  • compiler

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems and Management

Fingerprint

Dive into the research topics of 'An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings'. Together they form a unique fingerprint.

Cite this