An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning

Keisuke Sugiura, Hiroki Matsutani

Research output: Contribution to journalArticlepeer-review

Abstract

Path planning is a crucial component for realizing the autonomy of mobile robots. However, due to limited computational resources on mobile robots, it remains challenging to deploy state-of-the-art methods and achieve real-time performance. To address this, we propose P3Net (PointNet-based Path Planning Networks), a lightweight deep-learning-based method for 2D/3D path planning, and design an IP core (P3NetCore) targeting FPGA SoCs (Xilinx ZCU104). P3Net improves the algorithm and model architecture of the recently-proposed MPNet. P3Net employs an encoder with a PointNet backbone and a lightweight planning network in order to extract robust point cloud features and sample path points from a promising region. P3NetCore is comprised of the fully-pipelined point cloud encoder, batched bidirectional path planner, and parallel collision checker, to cover most part of the algorithm. On the 2D (3D) datasets, P3Net with the IP core runs 30.52-186.36x and 7.68-143.62x (15.69-93.26x and 5.30-45.27x) faster than ARM Cortex CPU and Nvidia Jetson while only consuming 0.255W (0.809W), and is up to 1278.14x (455.34x) power-efficient than the workstation. P3Net improves the success rate by up to 28.2% and plans a near-optimal path, leading to a significantly better tradeoff between computation and solution quality than MPNet and the state-of-the-art sampling-based methods.

Original languageEnglish
Pages (from-to)1442-1456
Number of pages15
JournalIEEE Transactions on Computers
Volume73
Issue number6
DOIs
Publication statusPublished - 2024 Jun 1

Keywords

  • FPGA
  • Path planning
  • PointNet
  • deep learning
  • neural path planning
  • point cloud processing

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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