TY - GEN
T1 - An on-chip self-powered non-volatile one-time-programmable memory system in standard CMOS technology
AU - Canada, Jorge
AU - Yoshida, Yui
AU - Miura, Hiroki
AU - Nakano, Nobuhiko
N1 - Funding Information:
ACKNOWLEDGMENT This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc., Rohm Corporation and Toppan Printing Corporation.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/11/23
Y1 - 2020/11/23
N2 - An on-chip self-powered memory system fully realizable in standard CMOS technology is presented. The memory cells consist of a MOS capacitor operated as an antifuse, which is written by applying high voltage between its terminals during tens of milliseconds. The full system comprises an on-chip solar cell, a cross coupled charge pump DC-DC converter, stacked MOSFET high voltage drivers and CMOS anti-fuse one-time programmable memory cells. The writing of each memory cell can be commanded through a digital signal provided by an on-chip control circuit or other on-chip sensors. The proposed memory system is intended to be integrated in small autonomous on-chip devices. This paper describes each of the components that build up the proposed system and demonstrates its feasibility through results of its implementation in 0.18 um CMOS technology.
AB - An on-chip self-powered memory system fully realizable in standard CMOS technology is presented. The memory cells consist of a MOS capacitor operated as an antifuse, which is written by applying high voltage between its terminals during tens of milliseconds. The full system comprises an on-chip solar cell, a cross coupled charge pump DC-DC converter, stacked MOSFET high voltage drivers and CMOS anti-fuse one-time programmable memory cells. The writing of each memory cell can be commanded through a digital signal provided by an on-chip control circuit or other on-chip sensors. The proposed memory system is intended to be integrated in small autonomous on-chip devices. This paper describes each of the components that build up the proposed system and demonstrates its feasibility through results of its implementation in 0.18 um CMOS technology.
KW - CMOS anti-fuse
KW - Low power consumption
KW - Non-volatile memory
KW - OTP memory
KW - On-chip
KW - Standard CMOS
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U2 - 10.1109/ICECS49266.2020.9294935
DO - 10.1109/ICECS49266.2020.9294935
M3 - Conference contribution
AN - SCOPUS:85099442606
T3 - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
BT - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020
Y2 - 23 November 2020 through 25 November 2020
ER -