Body bias control is an efficient means of balancing the trade-off between leakage power and performance especially for chips with silicon on thin buried oxide (SOTB), a type of FD-SOI technology. In this work, a method for finding the optimal combination of the supply voltage and body bias voltage to the core and memory is proposed and applied to a real micro-controller chip using SOTB CMOS technology. By obtaining several coefficients of equations for leakage power, switching power and operational frequency from the real chip measurements, the optimized voltage setting can be obtained for the target operational frequency. The power consumption lost by the error of optimization is 12.6% at maximum, and it can save at most 73.1% of power from the cases where only the body bias voltage is optimized. This method can be applied to the latest FD-SOI technologies.
|Title of host publication
|Proceedings of the International Symposium on Low Power Electronics and Design
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 2015 Sept 21
|20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015 - Rome, Italy
Duration: 2015 Jul 22 → 2015 Jul 24
|20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015
|15/7/22 → 15/7/24
- Body bias control
- Low power design
ASJC Scopus subject areas
- General Engineering