An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems

Peter Toth; Hiroki Ishikuro

doi:10.1145/3394885.3431644

An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems

Peter Toth, Hiroki Ishikuro

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work presents a novel control loop concept to adjust dynamically a differential ring oscillators (DRO) biasing in order to improve the phase noise performance (PN) in the ultra-low-power domain. Applying this proposed feedback system on any DRO with a tail current source is possible. The following paper presents the proposed concept and includes measurements of a 180 nm CMOS integrated prototype system, which underlines the feasibility of the discussed idea. Measurements show an up to 35 dBc/Hz phase noise improvement with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by about 430 % compared to fixed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz. University LSI Design Contest ASP-DAC 2021

Original language	English
Title of host publication	Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	9-10
Number of pages	2
ISBN (Electronic)	9781450379991
DOIs	https://doi.org/10.1145/3394885.3431644
Publication status	Published - 2021 Jan 18
Event	26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan Duration: 2021 Jan 18 → 2021 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
Country/Territory	Japan
City	Virtual, Online
Period	21/1/18 → 21/1/21

Keywords

amplitude feedback loop
phase-noise improving
time-mode circuit

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1145/3394885.3431644

Cite this

Toth, P., & Ishikuro, H. (2021). An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 (pp. 9-10). Article 3431644 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3394885.3431644

An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. / Toth, Peter; Ishikuro, Hiroki.
Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 9-10 3431644 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Toth, P & Ishikuro, H 2021, An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. in Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021., 3431644, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 9-10, 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021, Virtual, Online, Japan, 21/1/18. https://doi.org/10.1145/3394885.3431644

Toth P, Ishikuro H. An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 9-10. 3431644. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/3394885.3431644

Toth, Peter ; Ishikuro, Hiroki. / An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems. Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. pp. 9-10 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

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title = "An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems",

abstract = "This work presents a novel control loop concept to adjust dynamically a differential ring oscillators (DRO) biasing in order to improve the phase noise performance (PN) in the ultra-low-power domain. Applying this proposed feedback system on any DRO with a tail current source is possible. The following paper presents the proposed concept and includes measurements of a 180 nm CMOS integrated prototype system, which underlines the feasibility of the discussed idea. Measurements show an up to 35 dBc/Hz phase noise improvement with an active control loop. Moreover, the tuning range of the implemented ring oscillator is extended by about 430 % compared to fixed bias operation. These values are measured at a minimum oscillation power consumption of 55 pW/Hz. University LSI Design Contest ASP-DAC 2021",

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An up to 35dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems

Abstract

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Keywords

ASJC Scopus subject areas

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