An optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed whose parameters can be extracted with SPICE simulations. Therefore a device model can be precise, while keeping the optimization procedure simple and unchangeable in any device generation. With the proposed procedure, BiCMOS gate delays can be calculated quickly and optimized efficiently just by looking up design tables that are obtained easily and are applicable to any design with the same device technology. The sizing strategy of cascaded drivers is also studied. BiCMOS-BiCMOS cascaded buffers are optimized when the scale-up factor is e2.3, while BiCMOS-CMOS cascaded buffers become the fastest when the scale-up factor, e1.6, is employed. The strategy was successfully applied to the design of high-speed BiCMOS static-RAM (SRAM) macros for standard cell libraries.
|Number of pages
|Proceedings - IEEE International Symposium on Circuits and Systems
|Published - 1991 Dec 1
|1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore
Duration: 1991 Jun 11 → 1991 Jun 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering