Analytical single-electron transistor (SET) model for design and analysis of realistic SET circuits

In this work, we propose a compact, physically based, analytical single-electron transistor (SET) model suitable for the design and analysis of realistic SET circuits. The model is derived on the basis of the "orthodox" theory of correlated single-electron tunneling and the steady-state master equation method. The SET inverter characteristics are successfully calculated using the model implemented in the simulation program with integrated circuit emphasis (SPICE). The hybrid circuit of SETs with metal-oxide-semiconductor field-effect transistors (MOSFETs) is also successfully simulated. By utilizing the model, it is clarified that the drain-voltage-induced shift of the gate voltage dependence of SET current reaches one-half of the drain voltage in the case of a completely symmetric SET.