TY - GEN
T1 - Balanced dimension-order routing for k-ary n-cubes
AU - Montañana, Jose Miguel
AU - Koibuchi, Michihiro
AU - Matsutani, Hiroki
AU - Amano, Hideharu
PY - 2009
Y1 - 2009
N2 - Current Network-on-Chip (NoC) architectures sometimes employ mesh or torus topology with the dimensionorder routing. In this paper, we propose a deadlock-free routing algorithm, referred to as Balanced Dimension-Order Routing (BDOR), which provides the balanced minimal paths to each destination based on the simple routing regulations. Since the BDOR has the similar path regularity to that of the dimensionorder routing, its implementation can be lightweight, and most of its modules can be borrowed from the router for the dimension-order routing. Evaluation results show that the BDOR router increases by 3.4% hardware amount compared with the router for the dimension-order routing. Also show that the throughput of the BDOR outperforms on average up to 14% that of the dimension-order routing on two-dimensional mesh and torus.
AB - Current Network-on-Chip (NoC) architectures sometimes employ mesh or torus topology with the dimensionorder routing. In this paper, we propose a deadlock-free routing algorithm, referred to as Balanced Dimension-Order Routing (BDOR), which provides the balanced minimal paths to each destination based on the simple routing regulations. Since the BDOR has the similar path regularity to that of the dimensionorder routing, its implementation can be lightweight, and most of its modules can be borrowed from the router for the dimension-order routing. Evaluation results show that the BDOR router increases by 3.4% hardware amount compared with the router for the dimension-order routing. Also show that the throughput of the BDOR outperforms on average up to 14% that of the dimension-order routing on two-dimensional mesh and torus.
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U2 - 10.1109/ICPPW.2009.64
DO - 10.1109/ICPPW.2009.64
M3 - Conference contribution
AN - SCOPUS:77949535659
SN - 9780769538037
T3 - Proceedings of the International Conference on Parallel Processing Workshops
SP - 499
EP - 506
BT - ICPPW 2009 - The 38th International Conference Parallel Processing Workshops
T2 - 38th International Conference Parallel Processing Workshops, ICPPW 2009
Y2 - 22 September 2009 through 25 September 2009
ER -