Bit-line leakage compensation scheme for low-voltage SRAM's

Ken'ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda

Research output: Contribution to conferencePaperpeer-review

9 Citations (Scopus)


The induced bit-line leakage current (BLC) of an static random access memory (SRAM) by transistor leakage at low Vth and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. Vth can be lowered to 0.23 VDD in the 0.07 μm/1.0 V CMOS with this scheme as it was in the high-speed SRAM of the previous generations. SRAM operation speed can be improved by 25% at 0.9 V VDD compared with the case where this scheme is not applied.

Original languageEnglish
Number of pages2
Publication statusPublished - 2000
Externally publishedYes
Event2000 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 2000 Jun 152000 Jun 17


Other2000 Symposium on VLSI Circuits
CityHonolulu, HI, USA

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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