BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura

doi:10.1109/JSSC.2017.2778702

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Kota Ando
, Kodai Ueyoshi
, Kentaro Orimo
, Haruyoshi Yonekawa
, Shimpei Sato
, Hiroki Nakahara
, Shinya Takamaeda-Yamazaki
, Masayuki Ikebe
, Tetsuya Asai
, Tadahiro Kuroda
, Masato Motomura

Research output: Contribution to journal › Article › peer-review

139 Citations (Scopus)

Abstract

A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

Original language	English
Pages (from-to)	983-994
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	53
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2017.2778702
Publication status	Published - 2018 Apr

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Binary neural networks
in-memory processing
near-memory processing
neural networks
reconfigurable array
ternary neural networks

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2017.2778702

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Ando, K., Ueyoshi, K., Orimo, K., Yonekawa, H., Sato, S., Nakahara, H., Takamaeda-Yamazaki, S., Ikebe, M., Asai, T., Kuroda, T., & Motomura, M. (2018). BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE Journal of Solid-State Circuits, 53(4), 983-994. https://doi.org/10.1109/JSSC.2017.2778702

Ando, K, Ueyoshi, K, Orimo, K, Yonekawa, H, Sato, S, Nakahara, H, Takamaeda-Yamazaki, S, Ikebe, M, Asai, T, Kuroda, T & Motomura, M 2018, 'BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W', IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994. https://doi.org/10.1109/JSSC.2017.2778702

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abstract = "A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.",

keywords = "Binary neural networks, in-memory processing, near-memory processing, neural networks, reconfigurable array, ternary neural networks",

author = "Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura",

note = "Funding Information: Manuscript received August 3, 2017; revised October 16, 2017; accepted November 17, 2017. Date of publication December 19, 2017; date of current version March 23, 2018. This paper was approved by Guest Editor Makoto Ikeda. This work was supported by JST ACCEL, Japan, under Grant JPM-JAC1502. (Corresponding author: Kota Ando.) K. Ando, K. Ueyoshi, K. Orimo, S. Takamaeda-Yamazaki, M. Ikebe, T. Asai, and M. Motomura are with the Graduate School of Information Science and Technology, Hokkaido University, Sapporo 060-0814, Japan (e-mail: [email protected]). Publisher Copyright: {\textcopyright} 2012 IEEE.",

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AU - Orimo, Kentaro

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AU - Sato, Shimpei

AU - Nakahara, Hiroki

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AU - Kuroda, Tadahiro

AU - Motomura, Masato

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AB - A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

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BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Abstract

UN SDGs

Keywords

ASJC Scopus subject areas

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