TY - GEN
T1 - C4
T2 - 6th International Symposium on Computing and Networking Workshops, CANDARW 2018
AU - Shimura, Hideki
AU - Noda, Hiroyuki
AU - Amano, Hideharu
N1 - Funding Information:
Acknowledgment The study was supported by NEC Corporation. The design tools were supported by Xilinx Academic Program.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/12/26
Y1 - 2018/12/26
N2 - PCI Express (PCIe) has been widely used as an I/O bus connecting CPU and GPUs. In order to resolve the limitation of the number of PCIe ports, NEC Corporation developed ExpEther for expanding PCIe to Ethernet. Since Ethernet often becomes a bottleneck of communication, a conventional research proposed to implement a compression/decompression mechanism by using existing data compression mechanisms to reduce the size of data transferring on Ethernet. However, data compression mechanisms used in the research were only efficient for a limited input data pattern. In this paper, we proposed a novel data compression algorithm called C4, and implemented it on Xilinx Virtex-7 FPGA as an experimental environment of ExpEther. As a result, the proposed method can reduce the transfer time by 52.5%, superior to 49.7% with the conventional method. According to the evaluation of the hardware resource utilization rate, we showed that the proposed algorithm can be implemented in the FPGA used in the ExpEther NIC.
AB - PCI Express (PCIe) has been widely used as an I/O bus connecting CPU and GPUs. In order to resolve the limitation of the number of PCIe ports, NEC Corporation developed ExpEther for expanding PCIe to Ethernet. Since Ethernet often becomes a bottleneck of communication, a conventional research proposed to implement a compression/decompression mechanism by using existing data compression mechanisms to reduce the size of data transferring on Ethernet. However, data compression mechanisms used in the research were only efficient for a limited input data pattern. In this paper, we proposed a novel data compression algorithm called C4, and implemented it on Xilinx Virtex-7 FPGA as an experimental environment of ExpEther. As a result, the proposed method can reduce the transfer time by 52.5%, superior to 49.7% with the conventional method. According to the evaluation of the hardware resource utilization rate, we showed that the proposed algorithm can be implemented in the FPGA used in the ExpEther NIC.
KW - Compression algorithm
KW - ExpEther
KW - FPGA
UR - http://www.scopus.com/inward/record.url?scp=85061431074&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85061431074&partnerID=8YFLogxK
U2 - 10.1109/CANDARW.2018.00072
DO - 10.1109/CANDARW.2018.00072
M3 - Conference contribution
AN - SCOPUS:85061431074
T3 - Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018
SP - 356
EP - 362
BT - Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 27 November 2018 through 30 November 2018
ER -