Abstract
A snoop cache protocol is proposed for the WSI implementation which minimizes the access to the shared memory. In modified-Keio protocol, both write-invalidate and write-update type protocols can be used according to the nature of the shared data. It also supports the simple synchronization mechanism with Fetch&Dec operation and inter-processor interrupt. Detailed simulation with practical parallel applications demonstrates the efficiency of this proposed protocol.
| Original language | English |
|---|---|
| Pages (from-to) | 238-247 |
| Number of pages | 10 |
| Journal | Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon |
| Publication status | Published - 1995 Jan 1 |
| Externally published | Yes |
| Event | Proceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA Duration: 1995 Jan 18 → 1995 Jan 20 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Condensed Matter Physics