Cache line impact on 3D PDE solvers

Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)


Because performance disparity between processor and main memory is serious, it is necessary to reduce off-chip memory accesses by exploiting temporal locality. Loop tiling is a well-known optimization which enhances data locality. In this paper, we show a new cost model to select the best tile size in 3D partial differential equations. Our cost model carefully takes account of the effect of cache line. We present performance evaluation of our cost models. The evaluation results reveal the superiority of our cost model to other cost models proposed so far.

Original languageEnglish
Title of host publicationHigh Performance Computing - 4th International Symposium, ISHPC 2002, Proceedings
Number of pages9
Publication statusPublished - 2002
Externally publishedYes
Event4th International Symposium on High Performance Computing, ISHPC 2002 - Kansai Science City, Japan
Duration: 2002 May 152002 May 17

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2327 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference4th International Symposium on High Performance Computing, ISHPC 2002
CityKansai Science City

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science


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